1. Field of the Invention
The present invention relates to a communication network allowing transport of real-time information such as motion picture in conformity with standard specification of a high-speed serial bus such as IEEE1394 Serial Bus Standard and, in particular, to network synchronization techniques allowing data communication among nodes connected thereto.
2. Description of the Related Art
The IEEE1394 standard is an international standard for implementing a cost-effective and high-speed digital interface. An IEEE1394 interface provides high-speed data transport of several hundreds of megabits per second, a high affinity for real-time transport required for digital video data transmission, and usability features. Accordingly, the IEEE1394 digital interface is caused to provoke widespread attention as a network interface for both computer peripherals and consumer electronics including digital video cameras and digital television sets.
FIG. 1, as a typical example, shows a network for data transport in conformity with the IEEE1394 standard. In general, the IEEE1394 defines physical layer, link layer, transaction layer, and serial bus management. On these layers an application layer is usually implemented as an upper layer. In FIG. 1, those layers that do not directly relate to the present invention are omitted for the sake of simplicity.
As shown in FIG. 1, an IEEE1394 network is composed of a plurality of nodes each having physical layer (PHY) device, which are connected in cascade through predetermined cables. Here, the port of PHY device 10 is connected to a port of PHY device 11 by a cable 60 and the other port of the PHY device 11 is connected to a port of PHY device 12 by a cable 61.
An IEEE1394 PHY device has a repeater function of inputting data on one port and outputting the data on all other ports thereof. Accordingly, the network of FIG. 1 is physically formed in tree topology but logically in bus topology. Hereinafter, a PHY device is referred to as a PHY LSI (large scale integration) because a PHY device is usually available as an LSI.
A PHY LSI operates according to a clock signal generated by an external crystal oscillator. In FIG. 1, the respective PHY LSIs 10–12 have crystal oscillators 30–32 attached thereto.
The resonance frequency fτ of a crystal oscillator is 24.576 MHz with a permissible deviation of ±100 ppm (parts per million). The IEEE1394 standard defines transport rates: S100, S200, and S400, which correspond to 4×fr (98.304 Mbits per second), 8×fr (196.608 Mbits per second), and 16×fr (393.216 Mbits per second), respectively. Since a clock signal at each node is in free-running state without frequency synchronization control, the PHY LSIs 10–12 may be operating in accordance with different clock frequencies within the permissible deviation of 100 ppm.
To achieve real-time data transport in such an IEEE1394 PHY circumstance, an isochronous cycle mode has been introduced in the IEEE1394 standard. In the isochronous cycle mode, only a node that has obtained a necessary bandwidth and gotten the right to transmit can transmit an isochronous stream packet. Since the isochronous cycle occurs in a period of 125 μsec, it ensures real-time transport of a stream of data.
The isochronous cycle starts after transmission of a cycle start packet, which is transmitted by a node functioning as a cycle master. In FIG. 1, it is assumed that the node 50 is the cycle master. The cycle start packet includes time information at which the packet itself was transmitted. A cycle time register provides this time information. In this example, the cycle master 50 writes a value of its own cycle time register 40 on a cycle start packet when transmitting it to the IEEE1394 bus.
As shown in FIG. 2, a cycle time register has a length of 32 bits, which is divided into 7-bit second count field, 13-bit cycle count field, and 12-bit cycle offset field.
The cycle offset field is a counter which counts according to a physical layer clock of 24.576 MHz such that a counter value is incremented by one from 0 to 3071 before resetting to zero and starting again. Accordingly, the counter value is reset to zero at intervals of 125 μsec.
The cycle count field is a counter which counts at intervals of 125 μsec. Its counter value is incremented by one when the cycle offset field is reset to zero, from 0 to 7999 before resetting to zero and starting again, and therefore it is reset to zero at intervals of 1 second.
The second count field is a counter which counts at intervals of 1 second. Its counter value is incremented by one when the cycle count field is reset to zero, from 0 to 127 before resetting to zero and starting again.
In general, a cycle time register (40, 41, 42) is implemented in a space of a control and status register (CSR) provided in the serial bus management (not shown). Accordingly, in FIG. 1, a link layer LSI (20, 21, 22) is separated from a corresponding cycle time register (40, 41, 42). However, the cycle time register is usually also implemented in the link layer LSI. The link layer LSI (20, 21, 22) operates according to a clock frequency of 49.152 MHz, which is twice the physical layer clock frequency of 24.576 MHz. In the link layer LSI, the clock frequency of 49.152 MHz is divided by 2 to produce the physical layer clock frequency of 24.576 MHz, which causes the cycle time register to operate.
Any node other than the cycle master receives the cycle start packet including the time information from the cycle master and overwrites a clock cycle offset value of its own cycle time register with the received time information to synchronize to the cycle master. In this manner, the contents of the cycle time register of each node are adjusted ever time the cycle start packet is received at intervals of 125 μsec so as to establish time information synchronization of all nodes.
For example, as shown in FIGS. 3A–3C, the time information synchronization is performed among the nodes 50–52. In this example, it is assumed that the PHY clock frequency of the crystal oscillator 31 in the node 51 is higher than that of the crystal oscillator 30 in the node 50 (cycle master ) and the PHY clock frequency of the crystal oscillator 32 in the node 52 is lower than that of the crystal oscillator 30.
For the sake of simplicity, it is further assumed that the cycle start packet is transmitted when the cycle offset value of the cycle time register 40 is reset from 3071 to zero at the rising edge of the PHY clock and the time information written in the cycle start packet is a cycle offset value of zero, that the other nodes 51 and 52 receive the cycle start packet from the cycle master 50 without delay, and that the overwriting of the cycle offset at the nodes 51 and 52 is performed at the rising edge of the PHY clock.
At the node 51 operating at a higher clock frequency, as shown in FIG. 3B, the cycle offset value is continuously reset to zero twice, which means a delay of one clock, resulting in time adjustment with a maximum adjusted amount of one clock. Since one clock is about 40 nanosecond, frequency fluctuations (variations in cycle time register value) of up to about 320 ppm will occur with respect to a period of 125 μsec.
The contents of the cycle time register is used for real-time transport of audiovisual stream (AV stream) defined by IEC 61583 standard. To receive the AV stream, it is necessary for a receiving side to decode it by faithfully reproducing the video frame frequency and audio sampling frequency that were used at the transmitting side. However, these media-dependent frequencies do not synchronize with frequencies used in the IEEE1394 standard. To reproduce such frequency, the transmitting side transmits a packet of data attaching frequency information as a time stamp and the receiving side, when receiving the packet, looks at this time stamp to reproduce the frequency information. The IEC61883 standard defines that such time stamp information is determined depending on the cycle time register of the transmitting side.
However, when frequency fluctuations, that is, variations in cycle time register value occur at the receiving side due to the synchronization control of cycle time register as described above, the AV-stream-dependent frequencies such as sampling timing also vary, which adversely influences the quality of image and sound reproduced from the received AV stream. Therefore, an improved network synchronization technique is desired.
Further, in the P1394.1 working group of IEEE, efforts are moving ahead to make IEEE1394 bridge standardization for connecting a plurality of IEEE1394 buses to form a large network. In such a network environment, network-wide synchronization is needed to transfer real-time data over plural IEEE1394 buses, which will be described hereinafter with reference to FIG. 4.
As shown in FIG. 4, it is assumed that two bridges 70 and 71 connect three IEEE1394 buses 90–92, in each of which synchronization control is performed by a corresponding cycle master as described before. Since each cycle master is operating at its own clock frequency, a synchronization method is needed among the cycle masters to achieve network-wide synchronization.
In FIG. 4, a bridge has a plurality of portals, each of which is connected to a corresponding IEEE1394 bus. For example, the bridge 70 has portals 80a and 80B each connected to IEEE1394 buses 90 and 91. The IEEE1394 buses 90–92 have cycle masters 100–102 predetermined according to IEEE1394 standard. A portal may function as a cycle master because it also functions as an IEEE node. One of the cycle masters 100–102 is selected as a net cycle master that is a cycle master for the entire bridge network. Here, the cycle master 102 is designated as a net cycle master for the bridge network.
The other cycle masters 100 and 101 synchronize their own time information to the time information of the net cycle master 102 using the following procedure.
First, the portal 91B of the bridge 71 synchronizes its own time information to the net cycle master 102 using a cycle start packet received from the net cycle master 102. On the other hand, the other portal 81A of the bridge 71 synchronizes its own time information to the cycle master 101 using a cycle start packet received from the cycle master 101. Accordingly, the bridge 71 can detect a time deviation of the cycle master 101 from the net cycle master 102 by comparing the time information of the cycle master 101 to that of the net cycle master 102. When such a time deviation has been detected, the portal 81A transmits a control packet to the cycle master 101 to adjust the cycle time register of the cycle master 101.
As shown in FIG. 5, a control packet, which is also called a cycle master adjustment packet, is formed according to a special isochronous stream packet format having no data field. Because of no data field, the value of a data length field is zero. A combination of tag and channel fields designates this packet as a control packet for cycle time adjustment. Here, the tag and channel fields store “3” and “31”, respectively. A transaction code (tcode) field stores “10” to indicate that this packet is based on the isochronous stream packet format.
A synchronization code (sy) field stores a value designating an amount to be adjusted in the cycle time register of a cycle master receiving this packet. For example, when the synchronization code (sy) field stores a value of 1, a cycle master that has received the control packet elongates a period of the following isochronous cycle (125 μsec) by one cycle offset of about 40 nanoseconds. On the other hand, when the synchronization code (sy) field stores a value of 3, a cycle master that has received the control packet shortens a period of the following isochronous cycle (125 μsec) by one cycle offset of about 40 nanoseconds.
In this manner, the cycle master 101 can operate the bus 91 with the isochronous cycle synchronizing to that of the bus 92 connected to the net cycle master 102. Therefore, the bus 91 synchronizes to the bus 92. Since the synchronization control for the bridge network is designed to synchronize the isochronous cycle periods, the values of second count field and cycle count field of a bus do not always coincide with those of another bus (see FIG. 2).
The bridge 70/performs the same synchronization control as the bridge 71. The bus 90 synchronizes to the bus 91 that synchronizes the bus 92. Therefore, all the buses 90–92 synchronize. Such a synchronization method is disclosed in Japanese Patent Application Unexamined Publication Nos. P2000-307557A and P2000-32030A.
The synchronization control in the bridge network is performed by-appropriately elongating or shortening a period of isochronous cycle (125 μsec) by one cycle offset of about 40 nanoseconds, resulting in an instantaneous frequency fluctuation of approximately 320 ppm when adjusted. In addition, the synchronization control in the bridge network is performed by sequentially establishing synchronization from a bus to the adjacent bus to synchronize all the buses. As described above, frequency fluctuations due to the above synchronization control of isochronous cycle within an IEEE1394 bus or a bridge network composed of a plurality of IEEE1394 buses adversely influence the quality of transmission of a received real-time stream. Especially, in the case of the bridge network, frequency fluctuations may be accumulated every time the synchronization control is performed for one bridge, resulting in a large amount of frequency deviation. It is the same with other communication networks having a function of notifying time information at regular intervals.